OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 241

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 6410d 16h /
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 6410d 16h /
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 6410d 16h /
238 Defines fixed to use generic RAM by default. mohor 6422d 20h /
237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 6425d 02h /
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6425d 02h /
235 rev 4. mohor 6425d 16h /
234 Figure list assed to the revision 3. mohor 6426d 00h /
233 Revision 0.3 released. Some figures added. mohor 6426d 01h /
232 fpga define added. mohor 6430d 20h /
231 Description of Core Modules added (figure). mohor 6432d 21h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 6436d 18h /
229 case changed to casex. mohor 6436d 18h /
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 6436d 21h /
227 Changed BIST scan signals. tadejm 6436d 21h /
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6436d 23h /
225 Some minor changes. tadejm 6436d 23h /
224 Signals for a wave window in Modelsim. tadejm 6437d 00h /
223 Some code changed due to bug fixes. tadejm 6437d 00h /
222 This commit was manufactured by cvs2svn to create tag 'rel_6'. 6440d 22h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.