OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 244

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7218d 02h /
243 Late collision is not reported any more. tadejm 7218d 07h /
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 7218d 22h /
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 7218d 22h /
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7218d 22h /
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7218d 22h /
238 Defines fixed to use generic RAM by default. mohor 7231d 02h /
237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 7233d 07h /
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7233d 07h /
235 rev 4. mohor 7233d 22h /
234 Figure list assed to the revision 3. mohor 7234d 06h /
233 Revision 0.3 released. Some figures added. mohor 7234d 06h /
232 fpga define added. mohor 7239d 01h /
231 Description of Core Modules added (figure). mohor 7241d 03h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7244d 23h /
229 case changed to casex. mohor 7244d 23h /
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7245d 03h /
227 Changed BIST scan signals. tadejm 7245d 03h /
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7245d 05h /
225 Some minor changes. tadejm 7245d 05h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.