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246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 6522d 04h /
245 Rev 1.7. mohor 6522d 21h /
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 6523d 00h /
243 Late collision is not reported any more. tadejm 6523d 05h /
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 6523d 20h /
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 6523d 20h /
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 6523d 20h /
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 6523d 20h /
238 Defines fixed to use generic RAM by default. mohor 6536d 00h /
237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 6538d 05h /
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6538d 05h /
235 rev 4. mohor 6538d 20h /
234 Figure list assed to the revision 3. mohor 6539d 04h /
233 Revision 0.3 released. Some figures added. mohor 6539d 04h /
232 fpga define added. mohor 6543d 23h /
231 Description of Core Modules added (figure). mohor 6546d 01h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 6549d 21h /
229 case changed to casex. mohor 6549d 21h /
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 6550d 01h /
227 Changed BIST scan signals. tadejm 6550d 01h /

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