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Rev	Log message	Author	Age	Path
246	Since r_Rst bit is not used any more, default value is changed to 0xa000.	mohor	7851d 04h	/
245	Rev 1.7.	mohor	7851d 22h	/
244	r_Rst signal does not reset any module any more and is removed from the design.	mohor	7852d 00h	/
243	Late collision is not reported any more.	tadejm	7852d 05h	/
242	Late collision is reported only when not in the full duplex. Sample is taken (for status) as soon as MRxDV is not valid (regardless of the received byte cnt).	tadejm	7852d 20h	/
241	StartIdle state changed (not important the size of the packet). StartData1 activates only while ByteCnt is smaller than the MaxFrame.	tadejm	7852d 20h	/
240	All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.	tadejm	7852d 20h	/
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	7852d 20h	/
238	Defines fixed to use generic RAM by default.	mohor	7865d 00h	/
237	This commit was manufactured by cvs2svn to create tag 'rel_9'.		7867d 06h	/
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	7867d 06h	/
235	rev 4.	mohor	7867d 20h	/
234	Figure list assed to the revision 3.	mohor	7868d 04h	/
233	Revision 0.3 released. Some figures added.	mohor	7868d 05h	/
232	fpga define added.	mohor	7873d 00h	/
231	Description of Core Modules added (figure).	mohor	7875d 01h	/
230	This commit was manufactured by cvs2svn to create tag 'rel_8'.		7878d 22h	/
229	case changed to casex.	mohor	7878d 22h	/
228	This commit was manufactured by cvs2svn to create tag 'rel_7'.		7879d 01h	/
227	Changed BIST scan signals.	tadejm	7879d 01h	/
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	7879d 03h	/
225	Some minor changes.	tadejm	7879d 03h	/
224	Signals for a wave window in Modelsim.	tadejm	7879d 04h	/
223	Some code changed due to bug fixes.	tadejm	7879d 04h	/
222	This commit was manufactured by cvs2svn to create tag 'rel_6'.		7883d 02h	/
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	7883d 02h	/
220	This commit was manufactured by cvs2svn to create tag 'rel_5'.		7886d 03h	/
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	7886d 03h	/
218	Typo error fixed. (When using Bist)	mohor	7886d 05h	/
217	Bist supported.	mohor	7886d 05h	/

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