OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 247

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
247 This commit was manufactured by cvs2svn to create tag 'rel_10'. 6443d 16h /
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 6443d 16h /
245 Rev 1.7. mohor 6444d 10h /
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 6444d 12h /
243 Late collision is not reported any more. tadejm 6444d 18h /
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 6445d 08h /
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 6445d 08h /
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 6445d 08h /
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 6445d 08h /
238 Defines fixed to use generic RAM by default. mohor 6457d 12h /
237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 6459d 18h /
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6459d 18h /
235 rev 4. mohor 6460d 08h /
234 Figure list assed to the revision 3. mohor 6460d 17h /
233 Revision 0.3 released. Some figures added. mohor 6460d 17h /
232 fpga define added. mohor 6465d 12h /
231 Description of Core Modules added (figure). mohor 6467d 13h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 6471d 10h /
229 case changed to casex. mohor 6471d 10h /
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 6471d 14h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.