OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 248

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
248 wb_rst_i is used for MIIM reset. mohor 7831d 14h /
247 This commit was manufactured by cvs2svn to create tag 'rel_10'. 7834d 17h /
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7834d 17h /
245 Rev 1.7. mohor 7835d 10h /
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7835d 13h /
243 Late collision is not reported any more. tadejm 7835d 18h /
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7836d 09h /
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7836d 09h /
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7836d 09h /
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7836d 09h /
238 Defines fixed to use generic RAM by default. mohor 7848d 13h /
237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 7850d 18h /
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7850d 18h /
235 rev 4. mohor 7851d 09h /
234 Figure list assed to the revision 3. mohor 7851d 17h /
233 Revision 0.3 released. Some figures added. mohor 7851d 17h /
232 fpga define added. mohor 7856d 12h /
231 Description of Core Modules added (figure). mohor 7858d 14h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7862d 10h /
229 case changed to casex. mohor 7862d 10h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.