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249 This commit was manufactured by cvs2svn to create tag 'rel_11'. 7830d 04h /
248 wb_rst_i is used for MIIM reset. mohor 7830d 04h /
247 This commit was manufactured by cvs2svn to create tag 'rel_10'. 7833d 07h /
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7833d 07h /
245 Rev 1.7. mohor 7834d 01h /
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7834d 03h /
243 Late collision is not reported any more. tadejm 7834d 08h /
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7834d 23h /
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7834d 23h /
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7834d 23h /
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7834d 23h /
238 Defines fixed to use generic RAM by default. mohor 7847d 03h /
237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 7849d 09h /
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7849d 09h /
235 rev 4. mohor 7849d 23h /
234 Figure list assed to the revision 3. mohor 7850d 07h /
233 Revision 0.3 released. Some figures added. mohor 7850d 08h /
232 fpga define added. mohor 7855d 03h /
231 Description of Core Modules added (figure). mohor 7857d 04h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7861d 01h /
229 case changed to casex. mohor 7861d 01h /
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7861d 04h /
227 Changed BIST scan signals. tadejm 7861d 04h /
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7861d 06h /
225 Some minor changes. tadejm 7861d 06h /
224 Signals for a wave window in Modelsim. tadejm 7861d 07h /
223 Some code changed due to bug fixes. tadejm 7861d 08h /
222 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7865d 05h /
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7865d 05h /
220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7868d 06h /

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