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Rev	Log message	Author	Age	Path
256	TxDone and TxAbort changed so they're not propagated to the wishbone module when control frame is transmitted.	mohor	8211d 11h	/
255	TPauseRq synchronized to tx_clk.	mohor	8211d 11h	/
254	Temp version.	mohor	8212d 15h	/
253	r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.	mohor	8212d 17h	/
252	Just some updates.	tadejm	8212d 18h	/
251	When control frame (PAUSE) was sent, status was written in the eth_wishbone module and both TXB and TXC interrupts were set. Fixed. Only TXC interrupt is set.	mohor	8212d 18h	/
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	8212d 18h	/
249	This commit was manufactured by cvs2svn to create tag 'rel_11'.		8213d 18h	/
248	wb_rst_i is used for MIIM reset.	mohor	8213d 18h	/
247	This commit was manufactured by cvs2svn to create tag 'rel_10'.		8216d 21h	/
246	Since r_Rst bit is not used any more, default value is changed to 0xa000.	mohor	8216d 21h	/
245	Rev 1.7.	mohor	8217d 15h	/
244	r_Rst signal does not reset any module any more and is removed from the design.	mohor	8217d 17h	/
243	Late collision is not reported any more.	tadejm	8217d 22h	/
242	Late collision is reported only when not in the full duplex. Sample is taken (for status) as soon as MRxDV is not valid (regardless of the received byte cnt).	tadejm	8218d 13h	/
241	StartIdle state changed (not important the size of the packet). StartData1 activates only while ByteCnt is smaller than the MaxFrame.	tadejm	8218d 13h	/
240	All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.	tadejm	8218d 13h	/
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	8218d 13h	/
238	Defines fixed to use generic RAM by default.	mohor	8230d 17h	/
237	This commit was manufactured by cvs2svn to create tag 'rel_9'.		8232d 23h	/
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	8232d 23h	/
235	rev 4.	mohor	8233d 13h	/
234	Figure list assed to the revision 3.	mohor	8233d 21h	/
233	Revision 0.3 released. Some figures added.	mohor	8233d 22h	/
232	fpga define added.	mohor	8238d 17h	/
231	Description of Core Modules added (figure).	mohor	8240d 18h	/
230	This commit was manufactured by cvs2svn to create tag 'rel_8'.		8244d 15h	/
229	case changed to casex.	mohor	8244d 15h	/
228	This commit was manufactured by cvs2svn to create tag 'rel_7'.		8244d 18h	/
227	Changed BIST scan signals.	tadejm	8244d 18h	/

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