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Rev Log message Author Age Path
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 7852d 06h /
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.
mohor 7852d 18h /
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).
mohor 7853d 07h /
258 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7853d 08h /
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.
mohor 7853d 08h /
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.
mohor 7853d 08h /
255 TPauseRq synchronized to tx_clk. mohor 7853d 08h /
254 Temp version. mohor 7854d 11h /
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7854d 14h /
252 Just some updates. tadejm 7854d 14h /
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.
mohor 7854d 14h /
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 7854d 14h /
249 This commit was manufactured by cvs2svn to create tag 'rel_11'. 7855d 14h /
248 wb_rst_i is used for MIIM reset. mohor 7855d 14h /
247 This commit was manufactured by cvs2svn to create tag 'rel_10'. 7858d 17h /
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7858d 17h /
245 Rev 1.7. mohor 7859d 11h /
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7859d 13h /
243 Late collision is not reported any more. tadejm 7859d 19h /
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 7860d 09h /

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