OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 266

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
266 Flow control test almost finished. mohor 7815d 20h /
265 This commit was manufactured by cvs2svn to create tag 'rel_13'. 7816d 00h /
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.		 mohor 7816d 00h /
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7816d 12h /
262 Version 1.18 released.
MIIMRST (Reset of the MIIM module) not used any more in the MIIMODER
register. Control Frame bit (CF) added to the RX buffer descriptor. Control
frame detection section updated.		 mohor 7816d 12h /
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7816d 12h /
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7817d 00h /
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).		 mohor 7817d 13h /
258 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7817d 14h /
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.		 mohor 7817d 14h /
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.		 mohor 7817d 14h /
255 TPauseRq synchronized to tx_clk. mohor 7817d 14h /
254 Temp version. mohor 7818d 17h /
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7818d 20h /
252 Just some updates. tadejm 7818d 20h /
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7818d 20h /
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7818d 20h /
249 This commit was manufactured by cvs2svn to create tag 'rel_11'. 7819d 20h /
248 wb_rst_i is used for MIIM reset. mohor 7819d 20h /
247 This commit was manufactured by cvs2svn to create tag 'rel_10'. 7822d 23h /
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7822d 23h /
245 Rev 1.7. mohor 7823d 17h /
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7823d 19h /
243 Late collision is not reported any more. tadejm 7824d 01h /
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7824d 15h /
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7824d 15h /
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7824d 16h /
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7824d 16h /
238 Defines fixed to use generic RAM by default. mohor 7836d 20h /
237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 7839d 01h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.