URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 271

Rev	Log message	Author	Age	Path
251	When control frame (PAUSE) was sent, status was written in the eth_wishbone module and both TXB and TXC interrupts were set. Fixed. Only TXC interrupt is set.	mohor	7836d 20h	/
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	7836d 20h	/
249	This commit was manufactured by cvs2svn to create tag 'rel_11'.		7837d 20h	/
248	wb_rst_i is used for MIIM reset.	mohor	7837d 20h	/
247	This commit was manufactured by cvs2svn to create tag 'rel_10'.		7840d 23h	/
246	Since r_Rst bit is not used any more, default value is changed to 0xa000.	mohor	7840d 23h	/
245	Rev 1.7.	mohor	7841d 17h	/
244	r_Rst signal does not reset any module any more and is removed from the design.	mohor	7841d 19h	/
243	Late collision is not reported any more.	tadejm	7842d 00h	/
242	Late collision is reported only when not in the full duplex. Sample is taken (for status) as soon as MRxDV is not valid (regardless of the received byte cnt).	tadejm	7842d 15h	/