URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 272

Rev	Log message	Author	Age	Path
252	Just some updates.	tadejm	7829d 04h	/
251	When control frame (PAUSE) was sent, status was written in the eth_wishbone module and both TXB and TXC interrupts were set. Fixed. Only TXC interrupt is set.	mohor	7829d 04h	/
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	7829d 04h	/
249	This commit was manufactured by cvs2svn to create tag 'rel_11'.		7830d 05h	/
248	wb_rst_i is used for MIIM reset.	mohor	7830d 05h	/
247	This commit was manufactured by cvs2svn to create tag 'rel_10'.		7833d 08h	/
246	Since r_Rst bit is not used any more, default value is changed to 0xa000.	mohor	7833d 08h	/
245	Rev 1.7.	mohor	7834d 01h	/
244	r_Rst signal does not reset any module any more and is removed from the design.	mohor	7834d 03h	/
243	Late collision is not reported any more.	tadejm	7834d 09h	/