URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 312

Rev	Log message	Author	Age	Path
312	Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16.	tadejm	7441d 09h	/
311	Update script for running different file list files for different RAM models.	tadejm	7441d 09h	/
310	More signals.	tadejm	7441d 09h	/
309	Update file list files for different RAM models with byte select accessing.	tadejm	7441d 09h	/
308	Moved RAM model file path from sim_file_list.lst to this file.	tadejm	7441d 09h	/
307	This commit was manufactured by cvs2svn to create tag 'rel_24'.		7442d 07h	/
306	Lapsus fixed (!we -> ~we).	simons	7442d 07h	/
305	This commit was manufactured by cvs2svn to create tag 'rel_23'.		7464d 04h	/
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7464d 04h	/
303	This commit was manufactured by cvs2svn to create tag 'rel_22'.		7490d 14h	/
302	mbist signals updated according to newest convention	markom	7490d 14h	/
301	Update RxEnSync only when mrxdv_pad_i is inactive (LOW).	knguyen	7501d 06h	/
300	This commit was manufactured by cvs2svn to create tag 'rel_21'.		7548d 10h	/
299	Artisan RAMs added.	mohor	7548d 10h	/
298	This commit was manufactured by cvs2svn to create tag 'rel_20'.		7554d 05h	/
297	Artisan ram instance added.	simons	7554d 05h	/
296	This commit was manufactured by cvs2svn to create tag 'rel_19'.		7555d 08h	/
295	Few minor changes.	tadejm	7555d 08h	/
294	Added path to a file with distributed RAM instances for xilinx.	tadejm	7557d 09h	/
293	initial.	tadejm	7581d 06h	/