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Rev Log message Author Age Path
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 7392d 17h /
311 Update script for running different file list files for different RAM models. tadejm 7392d 17h /
310 More signals. tadejm 7392d 17h /
309 Update file list files for different RAM models with byte select accessing. tadejm 7392d 17h /
308 Moved RAM model file path from sim_file_list.lst to this file. tadejm 7392d 17h /
307 This commit was manufactured by cvs2svn to create tag 'rel_24'. 7393d 14h /
306 Lapsus fixed (!we -> ~we). simons 7393d 14h /
305 This commit was manufactured by cvs2svn to create tag 'rel_23'. 7415d 11h /
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7415d 11h /
303 This commit was manufactured by cvs2svn to create tag 'rel_22'. 7441d 22h /
302 mbist signals updated according to newest convention markom 7441d 22h /
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 7452d 14h /
300 This commit was manufactured by cvs2svn to create tag 'rel_21'. 7499d 17h /
299 Artisan RAMs added. mohor 7499d 17h /
298 This commit was manufactured by cvs2svn to create tag 'rel_20'. 7505d 13h /
297 Artisan ram instance added. simons 7505d 13h /
296 This commit was manufactured by cvs2svn to create tag 'rel_19'. 7506d 16h /
295 Few minor changes. tadejm 7506d 16h /
294 Added path to a file with distributed RAM instances for xilinx. tadejm 7508d 16h /
293 initial. tadejm 7532d 13h /

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