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Rev Log message Author Age Path
347 Added information about running with Icarus Verilog olof 5000d 18h /
346 Updated project location olof 5000d 20h /
345 Temporarily disable failing tests olof 5000d 22h /
344 bit 9 in phy control register is self clearing olof 5007d 00h /
343 Address miss should not be asserted on short frames olof 5010d 20h /
342 Added cast to avoid inequality when comparing different data types olof 5010d 20h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 5010d 20h /
340 Don't fail if log dir already exists olof 5011d 17h /
339 Added basic support for Icarus Verilog olof 5012d 17h /
338 root 5804d 22h /
337 root 5861d 00h /
336 Added old uploaded documents to new repository. root 5862d 04h /
335 New directory structure. root 5862d 04h /
334 Minor fixes for Icarus simulator. igorm 7310d 06h /
333 Some small fixes + some troubles fixed. igorm 7310d 18h /
332 Case statement improved for synthesys. igorm 7323d 23h /
331 Tests for delayed CRC and defer indication added. igorm 7339d 01h /
330 Warning fixes. igorm 7339d 01h /
329 Defer indication fixed. igorm 7339d 02h /
328 Delayed CRC fixed. igorm 7339d 02h /

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