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Rev Log message Author Age Path
347 Added information about running with Icarus Verilog olof 3176d 10h /
346 Updated project location olof 3176d 12h /
345 Temporarily disable failing tests olof 3176d 14h /
344 bit 9 in phy control register is self clearing olof 3182d 16h /
343 Address miss should not be asserted on short frames olof 3186d 12h /
342 Added cast to avoid inequality when comparing different data types olof 3186d 12h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 3186d 12h /
340 Don't fail if log dir already exists olof 3187d 10h /
339 Added basic support for Icarus Verilog olof 3188d 09h /
338 root 3980d 15h /
337 root 4036d 17h /
336 Added old uploaded documents to new repository. root 4037d 20h /
335 New directory structure. root 4037d 20h /
334 Minor fixes for Icarus simulator. igorm 5485d 22h /
333 Some small fixes + some troubles fixed. igorm 5486d 10h /
332 Case statement improved for synthesys. igorm 5499d 15h /
331 Tests for delayed CRC and defer indication added. igorm 5514d 17h /
330 Warning fixes. igorm 5514d 17h /
329 Defer indication fixed. igorm 5514d 18h /
328 Delayed CRC fixed. igorm 5514d 19h /

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