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Rev Log message Author Age Path
347 Added information about running with Icarus Verilog olof 4517d 19h /
346 Updated project location olof 4517d 21h /
345 Temporarily disable failing tests olof 4517d 22h /
344 bit 9 in phy control register is self clearing olof 4524d 00h /
343 Address miss should not be asserted on short frames olof 4527d 20h /
342 Added cast to avoid inequality when comparing different data types olof 4527d 20h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4527d 21h /
340 Don't fail if log dir already exists olof 4528d 18h /
339 Added basic support for Icarus Verilog olof 4529d 17h /
338 root 5321d 23h /
337 root 5378d 01h /
336 Added old uploaded documents to new repository. root 5379d 04h /
335 New directory structure. root 5379d 04h /
334 Minor fixes for Icarus simulator. igorm 6827d 07h /
333 Some small fixes + some troubles fixed. igorm 6827d 18h /
332 Case statement improved for synthesys. igorm 6841d 00h /
331 Tests for delayed CRC and defer indication added. igorm 6856d 01h /
330 Warning fixes. igorm 6856d 02h /
329 Defer indication fixed. igorm 6856d 03h /
328 Delayed CRC fixed. igorm 6856d 03h /

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