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Rev Log message Author Age Path
349 Make all parameters configurable from top level olof 3838d 06h /
348 Added option to dump VCD files olof 3839d 05h /
347 Added information about running with Icarus Verilog olof 3839d 06h /
346 Updated project location olof 3839d 08h /
345 Temporarily disable failing tests olof 3839d 09h /
344 bit 9 in phy control register is self clearing olof 3845d 11h /
343 Address miss should not be asserted on short frames olof 3849d 07h /
342 Added cast to avoid inequality when comparing different data types olof 3849d 07h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 3849d 08h /
340 Don't fail if log dir already exists olof 3850d 05h /
339 Added basic support for Icarus Verilog olof 3851d 04h /
338 root 4643d 10h /
337 root 4699d 12h /
336 Added old uploaded documents to new repository. root 4700d 15h /
335 New directory structure. root 4700d 15h /
334 Minor fixes for Icarus simulator. igorm 6148d 17h /
333 Some small fixes + some troubles fixed. igorm 6149d 05h /
332 Case statement improved for synthesys. igorm 6162d 11h /
331 Tests for delayed CRC and defer indication added. igorm 6177d 12h /
330 Warning fixes. igorm 6177d 13h /

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