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Rev Log message Author Age Path
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4663d 23h /
349 Make all parameters configurable from top level olof 4665d 00h /
348 Added option to dump VCD files olof 4665d 23h /
347 Added information about running with Icarus Verilog olof 4666d 00h /
346 Updated project location olof 4666d 02h /
345 Temporarily disable failing tests olof 4666d 03h /
344 bit 9 in phy control register is self clearing olof 4672d 05h /
343 Address miss should not be asserted on short frames olof 4676d 01h /
342 Added cast to avoid inequality when comparing different data types olof 4676d 01h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4676d 02h /
340 Don't fail if log dir already exists olof 4676d 23h /
339 Added basic support for Icarus Verilog olof 4677d 22h /
338 root 5470d 04h /
337 root 5526d 06h /
336 Added old uploaded documents to new repository. root 5527d 09h /
335 New directory structure. root 5527d 09h /
334 Minor fixes for Icarus simulator. igorm 6975d 11h /
333 Some small fixes + some troubles fixed. igorm 6975d 23h /
332 Case statement improved for synthesys. igorm 6989d 05h /
331 Tests for delayed CRC and defer indication added. igorm 7004d 06h /

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