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Rev Log message Author Age Path
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4748d 02h /
349 Make all parameters configurable from top level olof 4749d 02h /
348 Added option to dump VCD files olof 4750d 01h /
347 Added information about running with Icarus Verilog olof 4750d 02h /
346 Updated project location olof 4750d 04h /
345 Temporarily disable failing tests olof 4750d 06h /
344 bit 9 in phy control register is self clearing olof 4756d 08h /
343 Address miss should not be asserted on short frames olof 4760d 04h /
342 Added cast to avoid inequality when comparing different data types olof 4760d 04h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4760d 04h /
340 Don't fail if log dir already exists olof 4761d 01h /
339 Added basic support for Icarus Verilog olof 4762d 01h /
338 root 5554d 06h /
337 root 5610d 08h /
336 Added old uploaded documents to new repository. root 5611d 12h /
335 New directory structure. root 5611d 12h /
334 Minor fixes for Icarus simulator. igorm 7059d 14h /
333 Some small fixes + some troubles fixed. igorm 7060d 02h /
332 Case statement improved for synthesys. igorm 7073d 07h /
331 Tests for delayed CRC and defer indication added. igorm 7088d 09h /

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