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Rev Log message Author Age Path
360 Added partial implementation of the debug register from ORPSoC olof 3945d 05h /
359 Verilator linting fixes olof 3947d 07h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 3948d 21h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 3948d 21h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 3948d 23h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 3949d 00h /
354 Whitespace cleanup olof 3949d 00h /
353 Inherit fixes for bit width of constants from ORPSoC olof 3951d 02h /
352 Removed delayed assignments from rtl code olof 3955d 08h /
351 Turn defines into parameters in eth_cop olof 3963d 22h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3963d 22h /
349 Make all parameters configurable from top level olof 3964d 23h /
348 Added option to dump VCD files olof 3965d 22h /
347 Added information about running with Icarus Verilog olof 3965d 22h /
346 Updated project location olof 3966d 01h /
345 Temporarily disable failing tests olof 3966d 02h /
344 bit 9 in phy control register is self clearing olof 3972d 04h /
343 Address miss should not be asserted on short frames olof 3976d 00h /
342 Added cast to avoid inequality when comparing different data types olof 3976d 00h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 3976d 00h /
340 Don't fail if log dir already exists olof 3976d 22h /
339 Added basic support for Icarus Verilog olof 3977d 21h /
338 root 4770d 03h /
337 root 4826d 05h /
336 Added old uploaded documents to new repository. root 4827d 08h /
335 New directory structure. root 4827d 08h /
334 Minor fixes for Icarus simulator. igorm 6275d 10h /
333 Some small fixes + some troubles fixed. igorm 6275d 22h /
332 Case statement improved for synthesys. igorm 6289d 03h /
331 Tests for delayed CRC and defer indication added. igorm 6304d 05h /

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