Subversion Repositories ethmac

[/] - Rev 368


Filtering Options

Clear current filter

Rev Log message Author Age Path
368 dbg_dat0 only exist when `DEBUG_WISHBONE is set olof 2798d 18h /
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 2861d 16h /
366 Readded eth_top.v with a deprecation warning olof 2985d 20h /
365 Whitespace cleanup olof 2986d 19h /
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 2987d 16h /
363 quartus project files unneback 2988d 01h /
362 added Makefiles to build project unneback 2988d 01h /
361 created branch unneback unneback 2988d 01h /
360 Added partial implementation of the debug register from ORPSoC olof 2989d 00h /
359 Verilator linting fixes olof 2991d 02h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 2992d 16h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 2992d 16h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 2992d 18h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 2992d 19h /
354 Whitespace cleanup olof 2992d 19h /
353 Inherit fixes for bit width of constants from ORPSoC olof 2994d 21h /
352 Removed delayed assignments from rtl code olof 2999d 03h /
351 Turn defines into parameters in eth_cop olof 3007d 17h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3007d 17h /
349 Make all parameters configurable from top level olof 3008d 18h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2019, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.