URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 37

Rev	Log message	Author	Age	Path
17	Signal names changed on the top level for easier pad insertion (ASIC).	mohor	8297d 12h	/
16	"else" was missing within the always block in file eth_wishbonedma.v.	mohor	8304d 17h	/
15	A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). Include files fixed to contain no path. File names and module names changed ta have a eth_ prologue in the name. File eth_timescale.v is used to define timescale All pin names on the top module are changed to contain _I, _O or _OE at the end. Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O and Mdo_OE. The bidirectional signal must be created on the top level. This is done due to the ASIC tools.	mohor	8306d 11h	/
14	Unconnected signals are now connected.	mohor	8310d 16h	/
13	New directory structure. Files upodated and put together.	mohor	8313d 01h	/
12	Directory structure changed. Files checked and joind together.	mohor	8313d 04h	/
11	Directory structure changed. Files checked and joind together.	mohor	8313d 04h	/
10	Directory structure changed. Files checked and joind together.	mohor	8313d 04h	/
9	Documentation updated to be synchronized to the verilog files.	mohor	8340d 13h	/
8	Version 1.3. Status registers added. DMA channels 2 and 3 are not used any more. Things that are implementation specific were deleted out of the document.	mohor	8367d 17h	/