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Rev	Log message	Author	Age	Path
21	Status signals changed, Adress decoding changed, interrupt controller added.	mohor	8226d 06h	/
20	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8250d 03h	/
19	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8250d 03h	/
18	Few little NCSIM warnings fixed.	mohor	8263d 04h	/
17	Signal names changed on the top level for easier pad insertion (ASIC).	mohor	8290d 04h	/
16	"else" was missing within the always block in file eth_wishbonedma.v.	mohor	8297d 09h	/
15	A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). Include files fixed to contain no path. File names and module names changed ta have a eth_ prologue in the name. File eth_timescale.v is used to define timescale All pin names on the top module are changed to contain _I, _O or _OE at the end. Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O and Mdo_OE. The bidirectional signal must be created on the top level. This is done due to the ASIC tools.	mohor	8299d 03h	/
14	Unconnected signals are now connected.	mohor	8303d 08h	/
13	New directory structure. Files upodated and put together.	mohor	8305d 17h	/
12	Directory structure changed. Files checked and joind together.	mohor	8305d 20h	/

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