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Rev Log message Author Age Path
89 TX_BD_NUM, MAC_ADDR0 and MAC_ADDR1 register description
mohor 8016d 01h /
88 rx_fifo was not always cleared ok. Fixed. mohor 8022d 00h /
87 Status was not latched correctly sometimes. Fixed. mohor 8022d 02h /
86 Big Endian problem when sending frames fixed. mohor 8023d 09h /
85 Log info was missing. mohor 8028d 19h /
84 LinkFail signal was not latching appropriate bit. mohor 8028d 19h /
83 MAC address recognition was not correct (bytes swaped). mohor 8028d 19h /
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.
mohor 8028d 21h /
81 Typos fixed, INT_SOURCE and INT_MASK registers changed. mohor 8028d 21h /
80 Small fixes for external/internal DMA missmatches. mohor 8032d 23h /
79 RetryCntLatched was unused and removed from design mohor 8033d 00h /
78 WB_SEL_I was unused and removed from design mohor 8033d 00h /
77 Interrupts changed mohor 8033d 00h /
76 Interrupts changed in the top file mohor 8033d 00h /
75 r_Bro is used for accepting/denying frames mohor 8033d 00h /
74 Reset values are passed to registers through parameters mohor 8033d 00h /
73 Number of interrupts changed mohor 8033d 00h /
72 Retry is not activated when a Tx Underrun occured mohor 8037d 03h /
71 Address recognition system added. Buffer Descriptors changed. DMA section
changed. Ports changed.
mohor 8041d 05h /
70 Small fixes. mohor 8041d 06h /

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