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URL https://opencores.org/ocsvn/ethmac10g/ethmac10g/trunk

Subversion Repositories ethmac10g

[/] [ethmac10g/] [trunk/] - Rev 72

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Rev Log message Author Age Path
72 New directory structure. root 5545d 22h /ethmac10g/trunk/
71 Replay xilinx fifo with private fifo fisher5090 5879d 18h /trunk/
70 no message fisher5090 6543d 12h /trunk/
69 no message fisher5090 6543d 12h /trunk/
68 datasheet of management module fisher5090 6543d 23h /trunk/
67 modify mgmt_miim_rdy timing sequence fisher5090 6544d 07h /trunk/
66 comments added fisher5090 6544d 10h /trunk/
65 bad coding style, but works, will be modified later fisher5090 6544d 14h /trunk/
64 no message fisher5090 6547d 00h /trunk/
63 remove pad function added, using xilinx vp20 -6 as target FPGA, passes post place and route simulation fisher5090 6547d 00h /trunk/
62 no message fisher5090 6547d 07h /trunk/
61 no message fisher5090 6547d 08h /trunk/
60 change rxd_in, rxc_in and rxclk_in signals'name to xgmii_rxd, xgmii_rxc and xgmii_rxclk fisher5090 6547d 09h /trunk/
59 first version fisher5090 6547d 09h /trunk/
58 configuration vector select inband fcs or not fisher5090 6547d 15h /trunk/
57 both inband fcs and no inband fcs are OK fisher5090 6547d 15h /trunk/
56 no message fisher5090 6548d 06h /trunk/
55 testbench for normal frame and error frame fisher5090 6548d 07h /trunk/
54 removed fisher5090 6548d 07h /trunk/
53 testbench for normal and error frame fisher5090 6548d 11h /trunk/
52 modified the rx_good_frame and rx_bad_frame timing sequence fisher5090 6548d 11h /trunk/
51 modified fisher5090 6550d 15h /trunk/
50 good version fisher5090 6550d 15h /trunk/
49 datasheet for receive module fisher5090 6550d 15h /trunk/
48 no message fisher5090 6551d 07h /trunk/
47 no message fisher5090 6551d 11h /trunk/
46 receive engine datasheet fisher5090 6551d 23h /trunk/
45 first version fisher5090 6553d 09h /trunk/
44 no message fisher5090 6553d 09h /trunk/
43 no message fisher5090 6553d 13h /trunk/

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