URL https://opencores.org/ocsvn/fade_ether_protocol/fade_ether_protocol/trunk

Subversion Repositories fade_ether_protocol

[/] [fade_ether_protocol/] [trunk/] [stable_jumbo_frames_version/] [fpga/] [src/] [AFCK/] [AFCK_fade_top_8ch.vhd] - Rev 44

Rev	Log message	Author	Age	Path
44	Changed design for Kintex 7 based boards (AFCK, KC705) so that they use the VEXTPROJ environment for VCS friendly project management (described in http://doi.org/10.1117/12.2247944 )	wzab	2669d 20h	/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/src/AFCK/AFCK_fade_top_8ch.vhd
42	KC705 design upgraded to Vivado 2016.4 Corrrected indentation in a few files in AFCK design	wzab	2670d 01h	/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/src/AFCK/AFCK_fade_top_8ch.vhd
41	The AFCK project upgraded to Vivado 2016.4	wzab	2670d 02h	/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/src/AFCK/AFCK_fade_top_8ch.vhd
40	The "jumbo frame version" renamed from "experimental" to "stable".	wzab	2670d 07h	/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/src/AFCK/AFCK_fade_top_8ch.vhd
37	Added new design for AFCK board, which uses 8 10 Gbps links. Additionally added I2C control of the AFCK Si57x based clock. The I2C controller is driven via VIO blocks controlled by JTAG interface from Vivado Tcl console. Tcl scripts are in the fpga/src/AFCK/i2c_tools directory. To configure clock to 156.25MHz, and to route it to links, change directory to fpga/src/AFCK/i2c_tools and do "source start_10g_links.tcl". After the clock is reprogrammed, reconfigure the FPGA again (it seems, that there is a problem with reseting links after clock is reconfigured).	wzab	3271d 20h	/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/src/AFCK/AFCK_fade_top_8ch.vhd