URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] - Rev 90

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Rev	Log message	Author	Age	Path
90	- sin / cosine	robfinch	352d 20h	/ft816float/trunk/rtl/verilog2/
89	- fix compare in DFPTrunc96	robfinch	508d 08h	/ft816float/trunk/rtl/verilog2/
88	- DPFTrunc() function	robfinch	508d 12h	/ft816float/trunk/rtl/verilog2/
86	- improve divider *10	robfinch	523d 14h	/ft816float/trunk/rtl/verilog2/
85	- improve divider *10	robfinch	523d 14h	/ft816float/trunk/rtl/verilog2/
84	- improve DPD divider	robfinch	523d 17h	/ft816float/trunk/rtl/verilog2/
83	- sign of zero is positive	robfinch	523d 19h	/ft816float/trunk/rtl/verilog2/
82	- improved divider	robfinch	523d 20h	/ft816float/trunk/rtl/verilog2/
81	- timing delay on divide - change adder in multiply	robfinch	524d 05h	/ft816float/trunk/rtl/verilog2/
80	- improve decimal float divide	robfinch	524d 11h	/ft816float/trunk/rtl/verilog2/
79	- fix sticky infinity	robfinch	525d 19h	/ft816float/trunk/rtl/verilog2/
78	- BCD subtraction - scaleb function	robfinch	526d 06h	/ft816float/trunk/rtl/verilog2/
76	- adjust 9 to 7	robfinch	528d 06h	/ft816float/trunk/rtl/verilog2/
75	- add triple precision decimal float	robfinch	528d 12h	/ft816float/trunk/rtl/verilog2/
74	- added single precision combo logic only version of FMA	robfinch	636d 05h	/ft816float/trunk/rtl/verilog2/
73	- fix Karatsuba carry chain bug	robfinch	807d 05h	/ft816float/trunk/rtl/verilog2/
72	- fix: mult32x32 prod high order bits	robfinch	807d 08h	/ft816float/trunk/rtl/verilog2/
71	- added decimal float reciprocal estimate	robfinch	815d 04h	/ft816float/trunk/rtl/verilog2/
70	- fix carry out for BCD add / sub	robfinch	815d 11h	/ft816float/trunk/rtl/verilog2/
68	- added decimal float compare	robfinch	819d 10h	/ft816float/trunk/rtl/verilog2/

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Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] - Rev 90

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