| Rev |
Log message |
Author |
Age |
Path |
| 37 |
added firmware version 1.0 as eeprom image |
nussgipfel |
5119d 14h |
/ |
| 36 |
this is the release of the firmware version 1.0
it is considered as complete, fully functional and as we know bug free.
changelog since version 0.5:
- stand-alone mode fully working (writing to the spi flash and fpga configuration during start-up)
- added some more visual guidiance using the bi-color LED. we flash now the LED for all commands using one or the other memory slot in the spi flash, this is start-up configuration, writing to the spi flash (mem:data) and delete of a fpga configuration (mem:del)
- old externel usbtmc driver confirmed to be working with linux 2.6.33 |
nussgipfel |
5119d 16h |
/ |
| 35 |
immediate test version. stand-alone spi flash bug is away. was a bus conflict, because we modifie the spi bus pins at two different code locations.
just a backup at the moment. needs more testing before a stable release. |
nussgipfel |
5145d 15h |
/ |
| 34 |
a bit clean-up |
nussgipfel |
5153d 21h |
/ |
| 33 |
fixed in the bit file header analyse function. it was not possible to handle bit files (configure fpga, store into spi flash) when using USB 1.1 conections.
disabled the debug define in the firmware Makefile
removed the chipscope file from the GECKO3COM_simple project to get the logic utilisation of our core only. |
nussgipfel |
5159d 09h |
/ |
| 32 |
fixed a lot of warnings when building the doxygen firmware documentation ("make doc") |
nussgipfel |
5162d 16h |
/ |
| 31 |
added the scaned development documents to the doc folder |
nussgipfel |
5166d 11h |
/ |
| 30 |
done. |
nussgipfel |
5171d 06h |
/ |
| 29 |
some bugfixes and here and there some comment cleaning |
nussgipfel |
5171d 10h |
/ |
| 28 |
switched to work on the v1 production GECKO3main. the timing is a big issue
with the prototype system. the cabeling and the possibly bad influence of the
prototype board layout makes it impossible to run this core in sync with the
host transfers.
out transfer is fully working. always in sync with the transfers and reads all
tmc headers correctly.
abort handling in the core works as well. there were some fixes needed in the
firmware, not all IN FIFO buffer where flushed.
a lot of work was done for the IN transfer (fpga to pc). the in transfer
handling in GECKO3COM_simple_test.vhd is finished.
the GECKO3COM_simple_datapath/fsm is finished.
there is still an issue left but I think the problem is in the gpif_com
module. for long IN transfers, we still not receive the correct number of bytes.
it works great for all sort of short transfers.
Here I present a time measurement to show the achieved message throughput:
(Response message was 1 byte, total with header and align bytes was 16 byte)
time for i in {0..100000}; do cat /dev/usbtmc1 > /dev/null; done
real 5m45.706s
user 0m27.498s
sys 4m52.676s
This shows that we can read data from the fpga with a rate up to 290 Hz |
nussgipfel |
5173d 12h |
/ |
| 27 |
some of the problems are fixed now, some still remain.
all transfersize counter where wrong. they have to count the correct number of bytes transfered.
handling of a "short word" added, to be shure that all data (also when it is shorter than a word)
is transfered.
corrected some errors with the fifo write enable signals. |
nussgipfel |
5175d 16h |
/ |
| 26 |
basic in/out transfers working. tester consumes data and generates the test messages.
protocol handling is working. at the moment it gets out of sync for long data outs.
for in transfers, to less data is sent to the host, deadlock for long in transfers. |
nussgipfel |
5179d 06h |
/ |
| 25 |
small update in the comments |
nussgipfel |
5184d 13h |
/ |
| 24 |
first version of the GECKO3COM_simple_test that successfully synthesized.
debugging starts now.
fixed a small bug in the gpif_com_test due to the adding of the gpif_com_eom signal and the eom bit
flip-flop in the gpif_com module. |
nussgipfel |
5184d 13h |
/ |
| 23 |
GECKO3COM_simple_test designed and written.
added needed switches to the ucf files.
did some cleanup in the GECKO3_simple_* |
nussgipfel |
5186d 08h |
/ |
| 22 |
a lot of work is done for the GECKO3COM_simple IP core. datapath and fsm is designed and implemente,
top level is implemented. needs still some tweks but time to make a backup!
the simple ip core will be tested together with the GECKO3COM_simple_test. |
nussgipfel |
5187d 17h |
/ |
| 21 |
system is fully working and tested with big files over 4 Gbyte. there were some smaller bugs and glitches which caused
sometimes a deadlock. they are fixed now.
one was because the fx2 reads the done pin sometimes wrong during a long data
transfer. I don't now if this is because of crosstalk on my prototyping system or fpga internal weakness.
a simple debouncing (read again after 40 ms) did the trick.
changed firmware version to 0.5rc0, basically all features targeted for 0.5 are done. |
nussgipfel |
5202d 12h |
/ |
| 20 |
basic synchronous IN (fpga to host) transfer works.
detail changes:
-the scpi command "fpga:data" checks now, if the fpga is configured before it changes the context to the fpga. if the fpga is
not configured, it returns an "EXECUTE ERROR".
in the same way, the main_loop checks if the fpga looses his configuration. it disables the GPIF, switches the context back
to the fx2 if so. this is mainly to avoid undeterministic behaviour if you reconfigure the fpga via jtag.
-introduced the new signal "EOM" end of message from the "usb tmc protokoll interpreter" to the gpif_com module
-changed the GPIF waveform for the FIFO IN transfer to the new scheme.
-implemented the same waveform into the gpif_com_fsm.vhd. works well together.
-bugfixed the gpif_com_test.vhd. sends the new EOM signal, the response message generator works now as it should.
-added the missing AUTHORS README and COPYING (license) files to the core directory. |
nussgipfel |
5203d 10h |
/ |
| 19 |
found a pinning error in the series production documentation. fixed in the wiki and the core.
really stable host to fpga data transfer achieved. several time over 4Gbyte transfered. including switching to fpga to
host GPIF waveform to listen to possible fpga transfer tries. but fpga to host transfers still not finished.
the correct length of data is read from the gpif_fsm now. still untested data consitency when data flow throtling occours.
need bigger buffers to test this. will be done on a higher level. |
nussgipfel |
5211d 11h |
/ |
| 18 |
I achieved now stable OUT transfers (from the PC to the FPGA) with working throtling (when the FPGA consumes data slower than the host delivers).
The basics needed for this are implemented in the FPGA like handshaking with the FX2 and clock domain transistion from the Interface clock to the user defined system clock.
in the gpif_com_test.vhd is a message rom, containing a prepared answer message to generate an IN transfer. this is needed for the next step. |
nussgipfel |
5214d 20h |
/ |
