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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [GECKO3COM_simple.xise] - Rev 29

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29 some bugfixes and here and there some comment cleaning nussgipfel 5194d 11h /gecko3/trunk/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple.xise
28 switched to work on the v1 production GECKO3main. the timing is a big issue
with the prototype system. the cabeling and the possibly bad influence of the
prototype board layout makes it impossible to run this core in sync with the
host transfers.

out transfer is fully working. always in sync with the transfers and reads all
tmc headers correctly.

abort handling in the core works as well. there were some fixes needed in the
firmware, not all IN FIFO buffer where flushed.

a lot of work was done for the IN transfer (fpga to pc). the in transfer
handling in GECKO3COM_simple_test.vhd is finished.

the GECKO3COM_simple_datapath/fsm is finished.

there is still an issue left but I think the problem is in the gpif_com
module. for long IN transfers, we still not receive the correct number of bytes.

it works great for all sort of short transfers.


Here I present a time measurement to show the achieved message throughput:
(Response message was 1 byte, total with header and align bytes was 16 byte)

time for i in {0..100000}; do cat /dev/usbtmc1 > /dev/null; done

real 5m45.706s
user 0m27.498s
sys 4m52.676s

This shows that we can read data from the fpga with a rate up to 290 Hz		 nussgipfel 5196d 13h /gecko3/trunk/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple.xise
24 first version of the GECKO3COM_simple_test that successfully synthesized.
debugging starts now.

fixed a small bug in the gpif_com_test due to the adding of the gpif_com_eom signal and the eom bit
flip-flop in the gpif_com module.		 nussgipfel 5207d 14h /gecko3/trunk/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple.xise
18 I achieved now stable OUT transfers (from the PC to the FPGA) with working throtling (when the FPGA consumes data slower than the host delivers).
The basics needed for this are implemented in the FPGA like handshaking with the FX2 and clock domain transistion from the Interface clock to the user defined system clock.

in the gpif_com_test.vhd is a message rom, containing a prepared answer message to generate an IN transfer. this is needed for the next step.		 nussgipfel 5237d 21h /gecko3/trunk/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple.xise
14 reorganising and renaming the stuff in these project.

the core will get the name "GECKO3COM_" followed by the type "simple", "plb" or "opb"
to follow the naming in the GECKO3 wiki and to show the IP core interface.

duplicated fifo corecenerator files are merged together including a wrapper to easily supress synthesizer warnings
from unavailable, unused and unconnected pins.

the project is now organised in a way how the IP core and it's parts are beeing used. this means that the
low-level gpif access module is instantiated by the higher level modules and not the other way around.
this will make more sense when more parts of this IP core are finished (planning is finished, they have
to be implemented and tested now).		 nussgipfel 5265d 18h /gecko3/trunk/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple.xise
12 this is the version 0.4 of the GECKO3com IP core.

This is the last version from Andreas Habegger, the maintainer for this core is now Christoph Zimmermann		 nussgipfel 5280d 20h /gecko3/trunk/GECKO3COM/gecko3com-ip/core/usb_tmc_com.xise
11 initial add of the version 0.3 of the GECKO3com IP core. originaly developped by Andreas Habegger.

this commit is just for backup and to make the project progress visible because version 0.4 is also ready and will be commited in the next step.		 nussgipfel 5280d 21h /gecko3/trunk/GECKO3COM/gecko3com-ip/core/usb_tmc_com.xise

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