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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [GECKO3COM_simple_prototype.xise] - Rev 27

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27 some of the problems are fixed now, some still remain.

all transfersize counter where wrong. they have to count the correct number of bytes transfered.
handling of a "short word" added, to be shure that all data (also when it is shorter than a word)
is transfered.

corrected some errors with the fifo write enable signals.		 nussgipfel 5198d 17h /gecko3/trunk/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple_prototype.xise
26 basic in/out transfers working. tester consumes data and generates the test messages.
protocol handling is working. at the moment it gets out of sync for long data outs.
for in transfers, to less data is sent to the host, deadlock for long in transfers.		 nussgipfel 5202d 07h /gecko3/trunk/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple_prototype.xise
24 first version of the GECKO3COM_simple_test that successfully synthesized.
debugging starts now.

fixed a small bug in the gpif_com_test due to the adding of the gpif_com_eom signal and the eom bit
flip-flop in the gpif_com module.		 nussgipfel 5207d 14h /gecko3/trunk/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple_prototype.xise
23 GECKO3COM_simple_test designed and written.
added needed switches to the ucf files.

did some cleanup in the GECKO3_simple_*		 nussgipfel 5209d 09h /gecko3/trunk/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple_prototype.xise
22 a lot of work is done for the GECKO3COM_simple IP core. datapath and fsm is designed and implemente,
top level is implemented. needs still some tweks but time to make a backup!

the simple ip core will be tested together with the GECKO3COM_simple_test.		 nussgipfel 5210d 18h /gecko3/trunk/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple_prototype.xise
18 I achieved now stable OUT transfers (from the PC to the FPGA) with working throtling (when the FPGA consumes data slower than the host delivers).
The basics needed for this are implemented in the FPGA like handshaking with the FX2 and clock domain transistion from the Interface clock to the user defined system clock.

in the gpif_com_test.vhd is a message rom, containing a prepared answer message to generate an IN transfer. this is needed for the next step.		 nussgipfel 5237d 21h /gecko3/trunk/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple_prototype.xise
14 reorganising and renaming the stuff in these project.

the core will get the name "GECKO3COM_" followed by the type "simple", "plb" or "opb"
to follow the naming in the GECKO3 wiki and to show the IP core interface.

duplicated fifo corecenerator files are merged together including a wrapper to easily supress synthesizer warnings
from unavailable, unused and unconnected pins.

the project is now organised in a way how the IP core and it's parts are beeing used. this means that the
low-level gpif access module is instantiated by the higher level modules and not the other way around.
this will make more sense when more parts of this IP core are finished (planning is finished, they have
to be implemented and tested now).		 nussgipfel 5265d 17h /gecko3/trunk/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple_prototype.xise

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