URL https://opencores.org/ocsvn/gpio/gpio/trunk

Subversion Repositories gpio

[/] [gpio/] [tags/] [rel_10/] [bench/] [verilog/] - Rev 67

Rev	Log message	Author	Age	Path
65	New directory structure.	root	5537d 17h	/gpio/tags/rel_10/bench/verilog/
49	This commit was manufactured by cvs2svn to create tag 'rel_10'.		7464d 02h	/gpio/tags/rel_10/bench/verilog/
47	small "names" modification...	gorand	7464d 02h	/gpio/tags/rel_10/bench/verilog/
45	small changes, for VATS...	gorand	7464d 23h	/gpio/tags/rel_10/bench/verilog/
41	small changes, to satisfy VATS..	gorand	7475d 01h	/gpio/tags/rel_10/bench/verilog/
37	tests passed.	gorand	7483d 15h	/gpio/tags/rel_10/bench/verilog/
26	Removed zero padding as per Avi Shamli suggestion.	lampret	8090d 18h	/gpio/tags/rel_10/bench/verilog/
22	Fixed two typos.	lampret	8168d 22h	/gpio/tags/rel_10/bench/verilog/
21	Added RGPIO_INTS.	lampret	8168d 22h	/gpio/tags/rel_10/bench/verilog/
18	Updated timing and fixed some typing errors.	lampret	8209d 12h	/gpio/tags/rel_10/bench/verilog/
13	Changed VCD output location.	lampret	8266d 22h	/gpio/tags/rel_10/bench/verilog/
12	Changed gpio top level into gpio_top. Changed defines.v into gpio_defines.v.	lampret	8266d 23h	/gpio/tags/rel_10/bench/verilog/
11	More intensive verification.	lampret	8294d 17h	/gpio/tags/rel_10/bench/verilog/
8	Changed directory structure, port names and drfines.	lampret	8294d 17h	/gpio/tags/rel_10/bench/verilog/