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[/] [gpio/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 65

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Rev Log message Author Age Path
65 New directory structure. root 5540d 03h /gpio/tags/rel_12/rtl/verilog/
55 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7457d 13h /gpio/tags/rel_12/rtl/verilog/
52 ifndef directive is not supported by all tools. simons 7465d 08h /gpio/tags/rel_12/rtl/verilog/
36 bug fixed. all tests passed. gorand 7486d 01h /gpio/tags/rel_12/rtl/verilog/
34 added support for 8-bit access to registers. gorand 7490d 11h /gpio/tags/rel_12/rtl/verilog/
31 Bug fix. Interrupts were also asserted when condition was not met. lampret 7843d 02h /gpio/tags/rel_12/rtl/verilog/
29 Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC]. lampret 7850d 03h /gpio/tags/rel_12/rtl/verilog/
27 negedge flops are enabled by default. lampret 8039d 06h /gpio/tags/rel_12/rtl/verilog/
26 Removed zero padding as per Avi Shamli suggestion. lampret 8093d 04h /gpio/tags/rel_12/rtl/verilog/
25 Ports changed per Ran Aviram suggestions. lampret 8093d 04h /gpio/tags/rel_12/rtl/verilog/
24 Interrupt is asserted only when an input changes (code patch by Jacob Gorban) lampret 8097d 21h /gpio/tags/rel_12/rtl/verilog/
23 Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification. lampret 8151d 06h /gpio/tags/rel_12/rtl/verilog/
22 Fixed two typos. lampret 8171d 07h /gpio/tags/rel_12/rtl/verilog/
21 Added RGPIO_INTS. lampret 8171d 07h /gpio/tags/rel_12/rtl/verilog/
20 Fixing style. lampret 8184d 04h /gpio/tags/rel_12/rtl/verilog/
19 Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS) lampret 8184d 17h /gpio/tags/rel_12/rtl/verilog/
17 Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS. lampret 8211d 22h /gpio/tags/rel_12/rtl/verilog/
15 Fixed wb_err_o. lampret 8226d 22h /gpio/tags/rel_12/rtl/verilog/
14 Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v. lampret 8269d 06h /gpio/tags/rel_12/rtl/verilog/

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