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[/] [gpio/] [tags/] [rel_9/] [rtl/] [verilog/] - Rev 67

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Rev Log message Author Age Path
65 New directory structure. root 5532d 04h /gpio/tags/rel_9/rtl/verilog/
46 This commit was manufactured by cvs2svn to create tag 'rel_9'. 7459d 10h /gpio/tags/rel_9/rtl/verilog/
36 bug fixed. all tests passed. gorand 7478d 03h /gpio/tags/rel_9/rtl/verilog/
34 added support for 8-bit access to registers. gorand 7482d 12h /gpio/tags/rel_9/rtl/verilog/
31 Bug fix. Interrupts were also asserted when condition was not met. lampret 7835d 03h /gpio/tags/rel_9/rtl/verilog/
29 Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC]. lampret 7842d 04h /gpio/tags/rel_9/rtl/verilog/
27 negedge flops are enabled by default. lampret 8031d 08h /gpio/tags/rel_9/rtl/verilog/
26 Removed zero padding as per Avi Shamli suggestion. lampret 8085d 05h /gpio/tags/rel_9/rtl/verilog/
25 Ports changed per Ran Aviram suggestions. lampret 8085d 05h /gpio/tags/rel_9/rtl/verilog/
24 Interrupt is asserted only when an input changes (code patch by Jacob Gorban) lampret 8089d 22h /gpio/tags/rel_9/rtl/verilog/
23 Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification. lampret 8143d 07h /gpio/tags/rel_9/rtl/verilog/
22 Fixed two typos. lampret 8163d 09h /gpio/tags/rel_9/rtl/verilog/
21 Added RGPIO_INTS. lampret 8163d 09h /gpio/tags/rel_9/rtl/verilog/
20 Fixing style. lampret 8176d 05h /gpio/tags/rel_9/rtl/verilog/
19 Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS) lampret 8176d 19h /gpio/tags/rel_9/rtl/verilog/
17 Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS. lampret 8204d 00h /gpio/tags/rel_9/rtl/verilog/
15 Fixed wb_err_o. lampret 8219d 00h /gpio/tags/rel_9/rtl/verilog/
14 Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v. lampret 8261d 07h /gpio/tags/rel_9/rtl/verilog/

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