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[/] [gpio/] [trunk/] [rtl/] [verilog/] - Rev 66

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Rev Log message Author Age Path
65 New directory structure. root 5530d 14h /gpio/trunk/rtl/verilog
62 Reorganize core, add synchronization flops. simont 7228d 03h /gpio/trunk/rtl/verilog
60 Bugfixes when GPIO_RGPIO_ECLK/GPIO_RGPIO_NEC disabled, gpio oe name change and set to active-high according to spec andreje 7300d 03h /gpio/trunk/rtl/verilog
56 added ECLK and NEC registers, all tests passed. gorand 7439d 23h /gpio/trunk/rtl/verilog
52 ifndef directive is not supported by all tools. simons 7455d 18h /gpio/trunk/rtl/verilog
36 bug fixed. all tests passed. gorand 7476d 12h /gpio/trunk/rtl/verilog
34 added support for 8-bit access to registers. gorand 7480d 22h /gpio/trunk/rtl/verilog
31 Bug fix. Interrupts were also asserted when condition was not met. lampret 7833d 13h /gpio/trunk/rtl/verilog
29 Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC]. lampret 7840d 14h /gpio/trunk/rtl/verilog
27 negedge flops are enabled by default. lampret 8029d 17h /gpio/trunk/rtl/verilog
26 Removed zero padding as per Avi Shamli suggestion. lampret 8083d 15h /gpio/trunk/rtl/verilog
25 Ports changed per Ran Aviram suggestions. lampret 8083d 15h /gpio/trunk/rtl/verilog
24 Interrupt is asserted only when an input changes (code patch by Jacob Gorban) lampret 8088d 08h /gpio/trunk/rtl/verilog
23 Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification. lampret 8141d 16h /gpio/trunk/rtl/verilog
22 Fixed two typos. lampret 8161d 18h /gpio/trunk/rtl/verilog
21 Added RGPIO_INTS. lampret 8161d 18h /gpio/trunk/rtl/verilog
20 Fixing style. lampret 8174d 15h /gpio/trunk/rtl/verilog
19 Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS) lampret 8175d 04h /gpio/trunk/rtl/verilog
17 Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS. lampret 8202d 09h /gpio/trunk/rtl/verilog
15 Fixed wb_err_o. lampret 8217d 09h /gpio/trunk/rtl/verilog

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