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Subversion Repositories i2c

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Rev Log message Author Age Path
76 Updated filter_cnt generation rherveille 4202d 05h /
75 Fixed sSDA generation rherveille 4208d 01h /
74 Added SCL/SDA line filter rherveille 4346d 22h /
73 Fixed double wishbone write in a single access rherveille 4346d 22h /
72 Fixed AL generation
Added median filter on SDA and SCL inputs
rherveille 4346d 22h /
71 Fixed double wishbone write in a single access rherveille 4346d 22h /
70 Added old uploaded documents to new repository. root 4655d 01h /
69 Added old uploaded documents to new repository. root 4655d 16h /
68 New directory structure. root 4655d 16h /
67 Fixed slave_wait clocked event syntax rherveille 4688d 18h /
66 Fixed type iscl_oen instead of scl_oen rherveille 4703d 18h /
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 4704d 04h /
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 4704d 04h /
63 Added clock synchronization logic
Fixed slave_wait signal
rherveille 4704d 04h /
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 4704d 18h /
61 Removed synopsys link; it's not used rherveille 5359d 06h /
60 Added missing semicolons ';' on endif rherveille 5536d 02h /
59 fixed short scl high pulse after clock stretch rherveille 5541d 04h /
58 fixed (n)ack generation rherveille 5573d 05h /
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 5573d 05h /

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