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Rev Log message Author Age Path
12 no message rherveille 8395d 09h /
11 Changed RST_LVL define to parameter. rherveille 8398d 17h /
10 Created new directory structure.
Added Verilog version.
rherveille 8420d 13h /
9 Created directory structure (documentation, vhdl, verilog) rherveille 8490d 08h /
8 Created directory structure (documentation, vhdl, verilog) rherveille 8490d 08h /
7 added some remarks, fixed some sensitivity lists rherveille 8559d 11h /
6 fixed typo txt -> txr rherveille 8563d 15h /
5 fixed an incomplete sensitivity list on assign_dato process rherveille 8570d 13h /
4 WISHBONE I2C Master Core: initial release rherveille 8622d 16h /
3 This commit was manufactured by cvs2svn to create tag 'first'. 8684d 16h /
2 initial release rherveille 8684d 16h /
1 Standard project directories initialized by cvs2svn. 8684d 16h /

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