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Rev Log message Author Age Path
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7849d 00h /
23 *** empty log message *** rherveille 7976d 05h /
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7986d 11h /
21 no message rherveille 8072d 11h /
20 Added Appendix A rherveille 8072d 11h /
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8076d 08h /
18 no message rherveille 8103d 04h /
17 C-include file.
Initial release		 rherveille 8191d 08h /
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8203d 07h /
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8208d 06h /
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8208d 06h /
13 Fixed some synthesis warnings. rherveille 8219d 10h /
12 no message rherveille 8225d 02h /
11 Changed RST_LVL define to parameter. rherveille 8228d 09h /
10 Created new directory structure.
Added Verilog version.		 rherveille 8250d 06h /
9 Created directory structure (documentation, vhdl, verilog) rherveille 8320d 01h /
8 Created directory structure (documentation, vhdl, verilog) rherveille 8320d 01h /
7 added some remarks, fixed some sensitivity lists rherveille 8389d 04h /
6 fixed typo txt -> txr rherveille 8393d 07h /
5 fixed an incomplete sensitivity list on assign_dato process rherveille 8400d 06h /
4 WISHBONE I2C Master Core: initial release rherveille 8452d 09h /
3 This commit was manufactured by cvs2svn to create tag 'first'. 8514d 08h /
2 initial release rherveille 8514d 08h /
1 Standard project directories initialized by cvs2svn. 8514d 08h /

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