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Rev Log message Author Age Path
27 Cleaned up code rherveille 7826d 19h /
26 *** empty log message *** rherveille 7830d 03h /
25 Added timing tests to i2c_model.
Updated testbench.
rherveille 7857d 23h /
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7857d 23h /
23 *** empty log message *** rherveille 7985d 04h /
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7995d 10h /
21 no message rherveille 8081d 10h /
20 Added Appendix A rherveille 8081d 10h /
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.
rherveille 8085d 07h /
18 no message rherveille 8112d 03h /
17 C-include file.
Initial release
rherveille 8200d 07h /
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8212d 06h /
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.
rherveille 8217d 05h /
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.
rherveille 8217d 05h /
13 Fixed some synthesis warnings. rherveille 8228d 09h /
12 no message rherveille 8234d 01h /
11 Changed RST_LVL define to parameter. rherveille 8237d 08h /
10 Created new directory structure.
Added Verilog version.
rherveille 8259d 05h /
9 Created directory structure (documentation, vhdl, verilog) rherveille 8329d 00h /
8 Created directory structure (documentation, vhdl, verilog) rherveille 8329d 00h /
7 added some remarks, fixed some sensitivity lists rherveille 8398d 03h /
6 fixed typo txt -> txr rherveille 8402d 06h /
5 fixed an incomplete sensitivity list on assign_dato process rherveille 8409d 05h /
4 WISHBONE I2C Master Core: initial release rherveille 8461d 08h /
3 This commit was manufactured by cvs2svn to create tag 'first'. 8523d 07h /
2 initial release rherveille 8523d 07h /
1 Standard project directories initialized by cvs2svn. 8523d 07h /

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