URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] - Rev 29

Rev	Log message	Author	Age	Path
29	Core is now a Multimaster I2C controller	rherveille	7793d 00h	/
28	* empty log message *	rherveille	7818d 17h	/
27	Cleaned up code	rherveille	7818d 17h	/
26	* empty log message *	rherveille	7822d 01h	/
25	Added timing tests to i2c_model. Updated testbench.	rherveille	7849d 21h	/
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	7849d 21h	/
23	* empty log message *	rherveille	7977d 03h	/
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	7987d 08h	/
21	no message	rherveille	8073d 08h	/
20	Added Appendix A	rherveille	8073d 08h	/
19	Fixed some race conditions in the i2c-slave model. Added debug information. Added headers.	rherveille	8077d 05h	/
18	no message	rherveille	8104d 01h	/
17	C-include file. Initial release	rherveille	8192d 05h	/
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8204d 04h	/
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8209d 03h	/
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8209d 03h	/
13	Fixed some synthesis warnings.	rherveille	8220d 07h	/
12	no message	rherveille	8225d 23h	/
11	Changed RST_LVL define to parameter.	rherveille	8229d 06h	/
10	Created new directory structure. Added Verilog version.	rherveille	8251d 03h	/