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Rev Log message Author Age Path
13 Fixed some synthesis warnings. rherveille 8358d 14h /
12 no message rherveille 8364d 06h /
11 Changed RST_LVL define to parameter. rherveille 8367d 13h /
10 Created new directory structure.
Added Verilog version.
rherveille 8389d 10h /
9 Created directory structure (documentation, vhdl, verilog) rherveille 8459d 05h /
8 Created directory structure (documentation, vhdl, verilog) rherveille 8459d 05h /
7 added some remarks, fixed some sensitivity lists rherveille 8528d 08h /
6 fixed typo txt -> txr rherveille 8532d 12h /
5 fixed an incomplete sensitivity list on assign_dato process rherveille 8539d 10h /
4 WISHBONE I2C Master Core: initial release rherveille 8591d 13h /

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