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Rev Log message Author Age Path
39 Forgot an 'end if' :-/ rherveille 7610d 14h /
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.
rherveille 7613d 22h /
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.
rherveille 7650d 13h /
36 Fixed cmd_ack generation item (no bug). rherveille 7765d 14h /
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7799d 04h /
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7803d 03h /
33 Fixed a bug in the Command Register declaration. rherveille 7825d 12h /
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.
rherveille 7835d 11h /
31 Core is now a Multimaster I2C controller. rherveille 7839d 12h /
30 Small code simplifications rherveille 7839d 12h /
29 Core is now a Multimaster I2C controller rherveille 7839d 14h /
28 *** empty log message *** rherveille 7865d 06h /
27 Cleaned up code rherveille 7865d 06h /
26 *** empty log message *** rherveille 7868d 14h /
25 Added timing tests to i2c_model.
Updated testbench.
rherveille 7896d 10h /
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7896d 10h /
23 *** empty log message *** rherveille 8023d 16h /
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8033d 21h /
21 no message rherveille 8119d 22h /
20 Added Appendix A rherveille 8119d 22h /

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