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Rev Log message Author Age Path
39 Forgot an 'end if' :-/ rherveille 7652d 20h /
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.
rherveille 7656d 03h /
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.
rherveille 7692d 19h /
36 Fixed cmd_ack generation item (no bug). rherveille 7807d 20h /
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7841d 10h /
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7845d 08h /
33 Fixed a bug in the Command Register declaration. rherveille 7867d 18h /
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.
rherveille 7877d 17h /
31 Core is now a Multimaster I2C controller. rherveille 7881d 18h /
30 Small code simplifications rherveille 7881d 18h /
29 Core is now a Multimaster I2C controller rherveille 7881d 19h /
28 *** empty log message *** rherveille 7907d 12h /
27 Cleaned up code rherveille 7907d 12h /
26 *** empty log message *** rherveille 7910d 20h /
25 Added timing tests to i2c_model.
Updated testbench.
rherveille 7938d 16h /
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7938d 16h /
23 *** empty log message *** rherveille 8065d 22h /
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8076d 03h /
21 no message rherveille 8162d 03h /
20 Added Appendix A rherveille 8162d 03h /
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.
rherveille 8166d 00h /
18 no message rherveille 8192d 20h /
17 C-include file.
Initial release
rherveille 8281d 00h /
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8293d 00h /
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.
rherveille 8297d 22h /
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.
rherveille 8297d 22h /
13 Fixed some synthesis warnings. rherveille 8309d 03h /
12 no message rherveille 8314d 18h /
11 Changed RST_LVL define to parameter. rherveille 8318d 02h /
10 Created new directory structure.
Added Verilog version.
rherveille 8339d 22h /

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