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Rev Log message Author Age Path
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.
rherveille 8165d 23h /
18 no message rherveille 8192d 18h /
17 C-include file.
Initial release
rherveille 8280d 23h /
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8292d 22h /
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.
rherveille 8297d 21h /
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.
rherveille 8297d 21h /
13 Fixed some synthesis warnings. rherveille 8309d 01h /
12 no message rherveille 8314d 17h /
11 Changed RST_LVL define to parameter. rherveille 8318d 00h /
10 Created new directory structure.
Added Verilog version.
rherveille 8339d 21h /

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