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Rev	Log message	Author	Age	Path
41	This commit was manufactured by cvs2svn to create tag 'asyst_2'.		7551d 18h	/
40	Fix a blocking vs. non-blocking error in the wb_dat output mux.	rherveille	7551d 18h	/
39	Forgot an 'end if' :-/	rherveille	7571d 14h	/
38	Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. Fixed a potential bug in the byte controller's host-acknowledge generation.	rherveille	7574d 22h	/
37	Fixed a type in example 1 Changed 'RW' to 'W' in command register description. Changed 'RW' to 'W' in transmit register description.	rherveille	7611d 13h	/
36	Fixed cmd_ack generation item (no bug).	rherveille	7726d 14h	/
35	Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.	rherveille	7760d 05h	/
34	Fixed a few 'arbitration lost' bugs. VHDL version only.	rherveille	7764d 03h	/
33	Fixed a bug in the Command Register declaration.	rherveille	7786d 12h	/
32	Multi-master capabilities added to the core. Changed documentation accordingly. Updated some timing diagrams.	rherveille	7796d 11h	/
31	Core is now a Multimaster I2C controller.	rherveille	7800d 13h	/
30	Small code simplifications	rherveille	7800d 13h	/
29	Core is now a Multimaster I2C controller	rherveille	7800d 14h	/
28	* empty log message *	rherveille	7826d 06h	/
27	Cleaned up code	rherveille	7826d 06h	/
26	* empty log message *	rherveille	7829d 14h	/
25	Added timing tests to i2c_model. Updated testbench.	rherveille	7857d 11h	/
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	7857d 11h	/
23	* empty log message *	rherveille	7984d 16h	/
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	7994d 21h	/

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