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41 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7598d 05h /
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7598d 05h /
39 Forgot an 'end if' :-/ rherveille 7618d 01h /
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.
rherveille 7621d 09h /
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.
rherveille 7658d 00h /
36 Fixed cmd_ack generation item (no bug). rherveille 7773d 01h /
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7806d 16h /
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7810d 14h /
33 Fixed a bug in the Command Register declaration. rherveille 7832d 23h /
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.
rherveille 7842d 22h /
31 Core is now a Multimaster I2C controller. rherveille 7847d 00h /
30 Small code simplifications rherveille 7847d 00h /
29 Core is now a Multimaster I2C controller rherveille 7847d 01h /
28 *** empty log message *** rherveille 7872d 17h /
27 Cleaned up code rherveille 7872d 17h /
26 *** empty log message *** rherveille 7876d 01h /
25 Added timing tests to i2c_model.
Updated testbench.
rherveille 7903d 22h /
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7903d 22h /
23 *** empty log message *** rherveille 8031d 03h /
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8041d 08h /

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