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44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7611d 10h /
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7611d 10h /
42 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7621d 08h /
41 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7621d 08h /
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7621d 08h /
39 Forgot an 'end if' :-/ rherveille 7641d 03h /
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.
rherveille 7644d 11h /
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.
rherveille 7681d 03h /
36 Fixed cmd_ack generation item (no bug). rherveille 7796d 04h /
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7829d 18h /
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7833d 16h /
33 Fixed a bug in the Command Register declaration. rherveille 7856d 01h /
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.
rherveille 7866d 01h /
31 Core is now a Multimaster I2C controller. rherveille 7870d 02h /
30 Small code simplifications rherveille 7870d 02h /
29 Core is now a Multimaster I2C controller rherveille 7870d 03h /
28 *** empty log message *** rherveille 7895d 20h /
27 Cleaned up code rherveille 7895d 20h /
26 *** empty log message *** rherveille 7899d 04h /
25 Added timing tests to i2c_model.
Updated testbench.
rherveille 7927d 00h /
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7927d 00h /
23 *** empty log message *** rherveille 8054d 05h /
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8064d 11h /
21 no message rherveille 8150d 11h /
20 Added Appendix A rherveille 8150d 11h /
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.
rherveille 8154d 08h /
18 no message rherveille 8181d 04h /
17 C-include file.
Initial release
rherveille 8269d 08h /
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8281d 07h /
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.
rherveille 8286d 06h /

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