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Rev Log message Author Age Path
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7938d 15h /
23 *** empty log message *** rherveille 8065d 21h /
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8076d 02h /
21 no message rherveille 8162d 02h /
20 Added Appendix A rherveille 8162d 02h /
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.
rherveille 8165d 23h /
18 no message rherveille 8192d 19h /
17 C-include file.
Initial release
rherveille 8280d 23h /
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8292d 23h /
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.
rherveille 8297d 21h /

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