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Rev Log message Author Age Path
46 Fixed slave address MSB='1' bug rherveille 7495d 21h /
45 Added slave address configurability rherveille 7495d 21h /
44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7580d 23h /
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7580d 23h /
42 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7590d 21h /
41 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7590d 21h /
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7590d 21h /
39 Forgot an 'end if' :-/ rherveille 7610d 17h /
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.
rherveille 7614d 01h /
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.
rherveille 7650d 16h /
36 Fixed cmd_ack generation item (no bug). rherveille 7765d 17h /
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7799d 08h /
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7803d 06h /
33 Fixed a bug in the Command Register declaration. rherveille 7825d 15h /
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.
rherveille 7835d 14h /
31 Core is now a Multimaster I2C controller. rherveille 7839d 16h /
30 Small code simplifications rherveille 7839d 16h /
29 Core is now a Multimaster I2C controller rherveille 7839d 17h /
28 *** empty log message *** rherveille 7865d 09h /
27 Cleaned up code rherveille 7865d 09h /

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