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Subversion Repositories i2c

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Rev	Log message	Author	Age	Path
47	Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.	rherveille	7378d 16h	/
46	Fixed slave address MSB='1' bug	rherveille	7453d 17h	/
45	Added slave address configurability	rherveille	7453d 17h	/
44	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7538d 19h	/
43	Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'.	rherveille	7538d 19h	/
42	This commit was manufactured by cvs2svn to create tag 'asyst_3'.		7548d 17h	/
41	This commit was manufactured by cvs2svn to create tag 'asyst_2'.		7548d 17h	/
40	Fix a blocking vs. non-blocking error in the wb_dat output mux.	rherveille	7548d 17h	/
39	Forgot an 'end if' :-/	rherveille	7568d 13h	/
38	Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. Fixed a potential bug in the byte controller's host-acknowledge generation.	rherveille	7571d 21h	/
37	Fixed a type in example 1 Changed 'RW' to 'W' in command register description. Changed 'RW' to 'W' in transmit register description.	rherveille	7608d 12h	/
36	Fixed cmd_ack generation item (no bug).	rherveille	7723d 13h	/
35	Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.	rherveille	7757d 04h	/
34	Fixed a few 'arbitration lost' bugs. VHDL version only.	rherveille	7761d 02h	/
33	Fixed a bug in the Command Register declaration.	rherveille	7783d 11h	/
32	Multi-master capabilities added to the core. Changed documentation accordingly. Updated some timing diagrams.	rherveille	7793d 10h	/
31	Core is now a Multimaster I2C controller.	rherveille	7797d 12h	/
30	Small code simplifications	rherveille	7797d 12h	/
29	Core is now a Multimaster I2C controller	rherveille	7797d 13h	/
28	* empty log message *	rherveille	7823d 05h	/
27	Cleaned up code	rherveille	7823d 05h	/
26	* empty log message *	rherveille	7826d 13h	/
25	Added timing tests to i2c_model. Updated testbench.	rherveille	7854d 10h	/
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	7854d 10h	/
23	* empty log message *	rherveille	7981d 15h	/
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	7991d 20h	/
21	no message	rherveille	8077d 21h	/
20	Added Appendix A	rherveille	8077d 21h	/
19	Fixed some race conditions in the i2c-slave model. Added debug information. Added headers.	rherveille	8081d 17h	/
18	no message	rherveille	8108d 13h	/

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[/] - Rev 47

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