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Rev Log message Author Age Path
27 Cleaned up code rherveille 7823d 01h /
26 *** empty log message *** rherveille 7826d 09h /
25 Added timing tests to i2c_model.
Updated testbench.
rherveille 7854d 05h /
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7854d 05h /
23 *** empty log message *** rherveille 7981d 10h /
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7991d 16h /
21 no message rherveille 8077d 16h /
20 Added Appendix A rherveille 8077d 16h /
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.
rherveille 8081d 13h /
18 no message rherveille 8108d 09h /

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