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Subversion Repositories i2c

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Rev	Log message	Author	Age	Path
55	Fixed register overwrite issue. Removed full_case pragma, replaced it by a default statement.	rherveille	7007d 09h	/
54	Fixed scl, sda delay.	rherveille	7007d 09h	/
53	Fixed previous fix :) Made a variable vs signal mistake.	rherveille	7303d 06h	/
52	Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.	rherveille	7303d 07h	/
51	Fixed simulation issue when writing to CR register	rherveille	7357d 08h	/
50	* empty log message *	rherveille	7372d 03h	/
49	Added testbench	rherveille	7372d 03h	/
48	Fixed a bug in the arbitration-lost signal generation. VHDL version only.	rherveille	7373d 10h	/
47	Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.	rherveille	7382d 07h	/
46	Fixed slave address MSB='1' bug	rherveille	7457d 07h	/
45	Added slave address configurability	rherveille	7457d 07h	/
44	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7542d 10h	/
43	Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'.	rherveille	7542d 10h	/
42	This commit was manufactured by cvs2svn to create tag 'asyst_3'.		7552d 08h	/
41	This commit was manufactured by cvs2svn to create tag 'asyst_2'.		7552d 08h	/
40	Fix a blocking vs. non-blocking error in the wb_dat output mux.	rherveille	7552d 08h	/
39	Forgot an 'end if' :-/	rherveille	7572d 03h	/
38	Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. Fixed a potential bug in the byte controller's host-acknowledge generation.	rherveille	7575d 11h	/
37	Fixed a type in example 1 Changed 'RW' to 'W' in command register description. Changed 'RW' to 'W' in transmit register description.	rherveille	7612d 03h	/
36	Fixed cmd_ack generation item (no bug).	rherveille	7727d 04h	/
35	Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.	rherveille	7760d 18h	/
34	Fixed a few 'arbitration lost' bugs. VHDL version only.	rherveille	7764d 16h	/
33	Fixed a bug in the Command Register declaration.	rherveille	7787d 01h	/
32	Multi-master capabilities added to the core. Changed documentation accordingly. Updated some timing diagrams.	rherveille	7797d 01h	/
31	Core is now a Multimaster I2C controller.	rherveille	7801d 02h	/
30	Small code simplifications	rherveille	7801d 02h	/
29	Core is now a Multimaster I2C controller	rherveille	7801d 03h	/
28	* empty log message *	rherveille	7826d 20h	/
27	Cleaned up code	rherveille	7826d 20h	/
26	* empty log message *	rherveille	7830d 04h	/

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[/] - Rev 55

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