OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] - Rev 57

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal		 rherveille 6451d 04h /
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.		 rherveille 7004d 02h /
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.		 rherveille 7005d 04h /
54 Fixed scl, sda delay. rherveille 7005d 04h /
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7301d 02h /
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7301d 03h /
51 Fixed simulation issue when writing to CR register rherveille 7355d 03h /
50 *** empty log message *** rherveille 7369d 22h /
49 Added testbench rherveille 7369d 22h /
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7371d 06h /
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7380d 02h /
46 Fixed slave address MSB='1' bug rherveille 7455d 03h /
45 Added slave address configurability rherveille 7455d 03h /
44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7540d 05h /
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7540d 05h /
42 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7550d 03h /
41 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7550d 03h /
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7550d 03h /
39 Forgot an 'end if' :-/ rherveille 7569d 23h /
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7573d 07h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.