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Rev Log message Author Age Path
58 fixed (n)ack generation rherveille 6121d 13h /
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 6121d 13h /
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 6674d 11h /
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 6675d 13h /
54 Fixed scl, sda delay. rherveille 6675d 13h /
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 6971d 11h /
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 6971d 11h /
51 Fixed simulation issue when writing to CR register rherveille 7025d 12h /
50 *** empty log message *** rherveille 7040d 07h /
49 Added testbench rherveille 7040d 07h /
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7041d 15h /
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7050d 11h /
46 Fixed slave address MSB='1' bug rherveille 7125d 11h /
45 Added slave address configurability rherveille 7125d 11h /
44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7210d 14h /
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7210d 14h /
42 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7220d 12h /
41 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7220d 12h /
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7220d 12h /
39 Forgot an 'end if' :-/ rherveille 7240d 08h /

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