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Rev Log message Author Age Path
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 5606d 23h /
61 Removed synopsys link; it's not used rherveille 6261d 10h /
60 Added missing semicolons ';' on endif rherveille 6438d 07h /
59 fixed short scl high pulse after clock stretch rherveille 6443d 09h /
58 fixed (n)ack generation rherveille 6475d 10h /
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 6475d 10h /
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 7028d 08h /
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 7029d 10h /
54 Fixed scl, sda delay. rherveille 7029d 10h /
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7325d 08h /
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7325d 08h /
51 Fixed simulation issue when writing to CR register rherveille 7379d 09h /
50 *** empty log message *** rherveille 7394d 04h /
49 Added testbench rherveille 7394d 04h /
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7395d 12h /
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7404d 08h /
46 Fixed slave address MSB='1' bug rherveille 7479d 08h /
45 Added slave address configurability rherveille 7479d 08h /
44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7564d 11h /
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7564d 11h /

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